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Microchip Technology /ATSAME70N20B /MCAN0 /DBTP

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Interpret as DBTP

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DSJW0DTSEG20DTSEG10DBRP0 (DISABLED)TDC

TDC=DISABLED

Description

Data Bit Timing and Prescaler Register

Fields

DSJW

Data (Re) Synchronization Jump Width
DTSEG2

Data Time Segment After Sample Point
DTSEG1

Data Time Segment Before Sample Point
DBRP

Data Bit Rate Prescaler
TDC

Transmitter Delay Compensation

0 (DISABLED): Transmitter Delay Compensation disabled.

1 (ENABLED): Transmitter Delay Compensation enabled.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data